 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TEA6430 AUDIO CELLULAR MATRIX . . . . . . . 5 STEREO INPUTS - 4 STEREO OUTPUTS 3-STATE OPERATION FOR EACH OUTPUT GAIN OUTPUT CONTROL 0dB/2/4/6dB/MUTE FOR EACH VERY LOW NOISE AND DISTORTION I2C BUS CONTROL 4 SUB-ADDRESS FACILITY 90dB CROSSTALK BETWEEN ANY INPUT AND OUTPUT DESCRIPTION The TEA6430 switches 5 stereo inputs on 4 stereo outputs, providing the customer with high quality sound (low noise, low distortion). The 4 stereo outputs can be set separately in high impedance state, to enable parallel connection of several devices (up to 4). All functions are controlled through the I2C bus. PIN CONNECTIONS SHRINK 24 (Plastic Package) ORDER CODE : TEA6430 GND REF VCC L1 IN L2 IN L3 IN L4 IN L5 IN L1 OUT R1 OUT L2 OUT R2 OUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SDA SCL SUB R1 IN R2 IN R3 IN R4 IN R5 IN R4 OUT L4 OUT R3 OUT 6430-01.EPS L3 OUT May 1996 1/10 TEA6430 BLOCK DIAGRAM RIGHT INP UTS 21 20 19 18 17 G 3 STATES OUT 3 STATES OUT 3 STATES OUT 12 G 14 G 16 VS 3 C 2 24 S DA SUPPLY BUS DECODER 23 S CL 22 ADR GND 1 G 3 STATES OUT 3 STATES OUT 3 STATES OUT 3 STATES OUT 15 G 13 G 11 G 4 5 6 7 8 9 6430-02.EPS LEF T INP UTS The output loads have to be larger than 2k (typical 10k) and 1500pF ABSOLUTE MAXIMUM RATINGS Symbol VCC VI Toper Tstg Supply Voltage Voltage at Pin i to GND Operating Ambient Temperature Storage Temperature Parameter Value 12 0, VCC 0, + 70 -20, + 150 Unit V V o o LEFT OUTPUTS RIGHT OUTPUTS T E A 6 4 3 0 GAIN 3 STATES OUT 10 C C THERMAL DATA Symbol R th (j-a) Parameter Junction-ambient Thermal Resistance Value 75 Unit o C/W 2/10 6430-02.TBL 6430-01.TBL TEA6430 ELECTRICAL CHARACTERISTICS (VCC = 8V, Tamb = 25oC, RL = 10k, RG = 600, f = 1kHz, G = 0dB, VIN = 0.5VRMS ; 3-state is controlled by I2C bus, unless otherwise specified) Symbol SUPPLY VCC ICC RR Supply Voltage Supply Current Ripple Rejection VIN = 0.5VRMS, f = 1kHz 7.2 4 70 8 7 10.2 10 V mA dB Parameter Test Conditions Min. Typ. Max. Unit AUDIO INPUTS VIN VDC RI Max. Signal Amplitude Input DC Level Input Resistance 30 2 VCC/2 50 100 VRMS V k k 0.1 0.4 VCC B = 20-20kHz, flat, see note 2 B = 20-20kHz, R L = 2k f = 1kHz, output disabled VIN = 1VRMS , f = 1kHz d = 0.3% f = 1kHz f = 1kHz, see note 3 2 -85 -85 1500 -100 -0.5 85 0.01 2.3 0.05 VCC/2 2.5 0 +0.5 5 0.6 VCC mV V V dB dB % VRMS dB pF 6430-03.TBL AUDIO OUTPUTS R OUT ZHI VOFF VOUT VN G THD VCL CS CL Notes : Output Resistance Output "off" Impedance DC Offset Change Output DC Level Output Noise Voltage Gain Isolation "off" State Distortion Clipping Level L, R Channel Separation Crosstalk Audio Channels Load Capacitance f = 20kHz, output disabled Switching between inputs, see note 1 50 60 100 dB 1. DC offset change is less than maximum limit, in all configurations (one or several devices in parallel), provided that the reference Pins (P2) are all connected together. 2. Flat filter according to CCIR-468-4, B = 20Hz-20kHz 3. Measured from any selected output which contains no signal to a set of other outputs. 3/10 TEA6430 I2C BUS CHARACTERISTICS Symbol SCL VIL VIH ILI fSCL tR tF CI SDA VIL VIH ILI CI tR tF VOL tF CL TIMING tLOW tHIGH tSU, DAT tHD, DAT tSU, STO tBUF tHD, STA tSU, STA Clock Low Period Clock High Period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low-to High Transition 4.7 4.0 250 0 4.0 4.7 4.0 4.7 340 1.3 0.6 100 0 0.6 1.3 0.6 0.6 340 ms ms ns ns s s 6430-04.TBL 6430-03.EPS Parameter Test Conditions Standard Mode Min. Max. - 0.3 3.0 + 1.5 VCC + 0.5 + 10 100 1000 300 10 - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 1000 300 0.4 250 400 Fast Mode Min. Max. - 0.3 3.0 - 10 0 + 1.5 VCC + 0.5 + 10 400 300 300 10 - 0.3 3.0 - 10 + 1.5 VCC + 0.5 + 10 10 300 300 0.4 250 400 Unit Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Capacitance Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance VI = 0 to V DD 1.5V to 3V 1.5V to 3V V V A kHz ns ns pF V V A pF ns ns V ns pF - 10 0 VI = 0 to V DD 1.5V to 3V 1.5V to 3V IOL = 3mA 3V to 1.5V s s Figure 1 : I2C Bus Timing SDA t BUF t LOW tf SCL t HD,STA tr t HD,DAT t HIGH t SU,DAT SDA t SU,STA t SU,STO 4/10 TEA6430 I2C BUS SELECTION I2C Bus Slave Address Address Value A6 1 A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0 R/W 0 Sub-address I2C Symbol Vsub 1 2 3 4 Note : Parameter Slave address HEXA 98 9E 9C 9A Conditions Sub-address (see note) A1 A0 0 0 1 1 1 0 0 1 Pin 22 Voltage (typ.) Unit GND VCC 1/3 2/3 V V VCC VCC The first 3 levels are defined by connecting the sub-address pin to the appropriate level. Sub-address 4 will be selected when this pin is left open. Data Byte b7 T * * * * * * * * * * * * * * 0 1 b6 01 * * * * * * 0 0 1 1 * * * * * * b5 00 * * * * * * 0 1 0 1 * * * * * * b4 G1 * * * * * * * * * * 0 0 1 1 * * b3 G0 * * * * * * * * * * 0 1 0 1 * * b2 I2 0 0 0 0 1 1 * * * * * * * * * * b1 I1 0 0 1 1 0 0 * * * * * * * * * * b0 I0 0 1 0 1 0 1 * * * * * * * * * * Action IN1 IN2 IN3 IN4 IN5 Mute OUT1 OUT2 OUT3 OUT4 6dB 4dB 2dB 0dB Low impedance Tri-state Input Select Output Select Gain Tri-state Example : 00111100 enables L(R)2 out and connect it with a gain of 0dB to L(R)5 in. Power On Reset When active : outputs in 3-state. All outputs are disabled and L(R)5 is selected to drive all outputs. Gain = 0dB. Symbol Reset Start of Reset End of Reset Parameter Conditions Incr. VCC Decr. VCC Incr. VCC Min. Typ. Max. 2.5 4.2 4.5 Unit V V V 5/10 TEA6430 TYPICAL PERFORMANCES Figure 1 : 10 Supply Current as a Function of Supply Voltage Figure 2 : SUPPLYCURRENT (mA) 8 Supply Current as a Function of Temperature V C C = 8V All outputs enabled SUPPLY CURRENT (mA) 9 8 T A = 25C All outputs enabled 7 7 6 6430-04.EPS 6 5 7 8 9 10 11 12 5 -20 0 20 40 60 80 SUPPLY VOLTAGE (V) TEMPERATURE (C) Figure 3 : RIPPLE REJECTION (dB) 89 Ripple Rejection as a Function of Supply Voltage Figure 4 : RIPPLEREJECTION(dB) 88 Ripple Rejection as a Function of Temperature 87 Gain = 0dB V IN = 600mV RMS T A = 25C 87 86 85 84 85 V C C = 8V Gain = 0dB f = 1kHz A ll outputs enabled 0 20 40 60 80 6430-07.EPS 6430-06.EPS 83 7 8 9 10 11 12 SUPPLY VOLTAGE (V) 83 -20 TEMPERATURE (C) Figure 5 : RIPPLE REJECTION (dB) 90 85 80 75 70 65 0 Ripple Rejection as a Function of Gain VC C = 8V T A = 25C VIN = 600m VRMS Figure 6 : 3.7 CLIPPING LEVEL ( V RMS ) Clipping Level as a Function of Supply Voltage 3.5 3.3 3.1 2.9 2.7 2.5 2.3 T A = 25C Distortion = 0.3% Gain = 0dB 2 GAIN (dB) 4 6 6430-08.EPS 7 8 9 10 11 12 SUPPLY VOLTAGE (V) 6/10 6430-09.EPS 2.1 1.9 6430-05.EPS TEA6430 TYPICAL PERFORMANCES (continued) Figure 7 : 1 Distortion as a Function of Input Level Figure 8 : 0.05 Distortion as a Function of Gain DISTORTION RATE (%) DISTORTION RATE (%) 0.8 0.6 T A = 25C VCC = 8V f = 1kHz Gain = 0dB 0.04 0.03 T A = 25C VC C = 8V f = 1kHz VOUT = 1 VRMS 0.4 0.2 6430-10.EPS 0.02 0.01 6430-11.EPS 6430-13.EPS 0 0.4 0.8 1.2 1.6 VIN - VRMS (V) 2 2.4 0 2 GAIN (dB) 4 6 Figure 9 : CROSSTALKLEVEL(dB) 99 95 91 87 83 Crosstalk Level as a Function of Frequency (Gain = 0dB) VCC = 8V Gain = 0dB VOUT = 2 VRMS TA = 25C Figure 10 : Crosstalk Level as a Function of Frequency (Gain = 6dB) CROSSTALKLEVEL(dB) 91 89 87 85 83 81 79 77 0 4 8 12 16 22 FREQUENCY (kHz) VCC = 8V Gain = 6dB TA = 25C 0 4 8 12 16 22 FREQUENCY (kHz) 6430-12.EPS 79 7/10 TEA6430 PIN CONFIGURATIONS Figure 11 : Audio IN Figure 12 : Audio OUT V CC TRI-STATE V CC TRI-STATE Pins 4 - 5 - 6 - 7 - 8 17 - 18 - 19 - 20 - 21 L (R) x in x = 1, 2, 3, 4 Pins 9 - 10 11 - 12- 13 14 - 15 - 16 L (R) x out x = 1, 2, 3, 4 50k Matrix Point V CC /2 6430-14.EPS TRI-STATE 10k Figure 13 : PROG Figure 14 : Bus Inputs V CC VC C 20k ESD PROT. 22 VREFi 40k to CMOS Pins 23 - 24 V REF to CMOS X4 3 TIMES IN // 6430-16.EPS ACKN 6430-17.EPS For SDA only 8/10 6430-15.EPS TEA6430 TYPICAL APPLICATION V CC (+8V) 1 100nF C1 C2 24 23 SDA SCL 2 3 4 5 6 I2 C LEFT INPUTS [1, 5] C3 C4 C5 7 8 9 10 11 12 T E A 6 4 3 0 22 21 20 19 18 17 16 15 14 13 C25 C24 C27 C26 C28 RIGHT INPUTS [1, 5] 22F 1 100nF 24 23 SDA SCL VCC C22 2 3 I2 C C6 C7 4 5 6 RIGHT INPUTS [6, 10] C8 C9 C10 7 8 9 10 11 12 T E A 6 4 3 0 22 21 20 19 18 17 16 15 14 13 C23 C21 C20 C19 RIGHT INPUTS [6, 10] C11 C12 C13 C14 C15 C16 C17 C18 * C1 to C28 = 4.7F OUT 1 OUT 2 OUT 3 OUT 4 9/10 6430-18.EPS R L R L R L R L TEA6430 PACKAGE MECHANICAL DATA 24 PINS - PLASTIC SHRINK DIP E E1 A1 A2 Stand-off B B1 e e1 e2 L c D E 24 13 F .015 0,38 A 1 12 e3 SDIP24 e2 Dimensions A A1 A2 B B1 C D E E1 e e1 e2 e3 L Min. 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10 Millimeters Typ. Max. 5.08 4.57 0.56 1.14 0.38 23.11 8.64 6.86 Min. 0.020 0.120 0.0142 0.030 0.0090 0.890 0.30 0.240 Inches Typ. Max. 0.20 0.180 0.0220 0.045 0.0150 0.910 0.340 0270 3.30 0.46 1.02 0.25 22.86 6.40 1.778 7.62 0.130 0.0181 0.040 0.0098 0.90 0.252 0.070 0.30 2.54 3.30 0.10 0.130 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 10/10 SDIP24.TBL 10.92 1.52 3.81 0.430 0.060 0.150 PMSDIP24.EPS Gage Plane |
Price & Availability of TEA6430
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |